Department of Computer Science & Engineering
The Chinese University of Hong Kong
Shatin, N.T., Hong Kong
| fyuan AT cse.cuhk.edu.hk | |
| Phone | (+852) 31634265 |
| Office | Room 506, Ho Sin Hang Build |
Mr. Feng Yuan is now a Ph.D. candidate at The Chinese University of Hong Kong, in the Computer Science & Engineering department. He is working in the VLSI EDA/Testing Laboratory under the supervision of Professor Qiang Xu. Before joining CUHK, he obtained his B.S. degree in 2006 from Chu Kochen Honor College of Zhejiang University, China.
His research interests include VSLI testing, fault-tolerant computing and post-silicon debug
Referred Conference Papers
[C14] F. Yuan, X. Liu and Q. Xu, "X-Tracer: A Reconfigurable X-Tolerant Trace Compressor for Silicon Debug", accepted for publication in Proc. ACM/IEEE Design Automation Conference (DAC), Jun. 2012.
[C13]R. Ye, F. Yuan, H. Zhou and Q. Xu, "Clock Skew Scheduling for Timing Speculation", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Mar. 2012.
[C12] F. Yuan, X. Liu and Q. Xu, "Pseudo-Functional Testing for Small Delay Defects Considering Power Supply Noise Effects", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2011. (acceptance rate: 106/349 = 30.4%)
[C11] R. Ye, F. Yuan and Q. Xu, "Online Clock Skew Tuning for Timing Speculation", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2011. (acceptance rate: 106/349 = 30.4%)
[C10] Y. Liu, F. Yuan and Q. Xu, "Re-Synthesis for Cost-Efficient Circuit-Level Timing Speculation", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 158-163, June 2011. (acceptance rate: 156/690 = 22.6%)
[C9] F. Yuan and Q. Xu, "On Timing-Independent False Path Identification", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 532-535, Nov. 2010. (acceptance rate: 108/360 = 30.0%)
[C8] X. Liu, Y. Zhang, F. Yuan and Q. Xu, "Layout-Aware Pseudo-Functional Testing for Critical Paths Considering Power Supply Noise Effects", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 1432-1437, March 2010. (acceptance rate: ~25%)
[C7] Y. Zhang, L. Huang, F. Yuan and Q. Xu, "Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks", Proc. IEEE Asian Test Symposium (ATS), pp. 460-465, Nov. 2009.
[C6] F. Yuan and Q. Xu, "Compression-Aware Pseudo-Functional Testing", Proc. IEEE International Test Conference (ITC), paper 9.1, Nov. 2009.
[C5] F. Yuan and Q. Xu, "On Systematic Illegal State Identification for Pseudo-Functional Testing", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 702-707, July 2009. (acceptance rate: 148/682 = 21.7%)
[C4] L. Huang, F. Yuan and Q. Xu, "Lifetime Reliability-Aware Task Allocation and Scheduling for MPSoC Platforms", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 51-56, Apr. 2009. (acceptance rate: 226/965 = 23.4%)
[C3] F. Yuan and Q. Xu, "SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects", Proc. IEEE International Test Conference (ITC), paper 26.2, Oct. 2008.
[C2] L. Huang, F. Yuan, and Q. Xu, "On Reliable Modular Testing with Vulnerable Test Access Mechanisms", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 834-839, June 2008. (acceptance rate: 147/639 = 23.0%)
[C1] F. Yuan, L. Huang and Q. Xu, "Re-Examining the Use of Network-on-Chip as Test Access Mechanism", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 808-811, Mar. 2008. (interactive presentation, acceptance rate: (198+46)/837 = 29.2%)
Referred Journal Articles
[J1] L. Huang, F. Yuan, and Q. Xu, "On Task Allocation and Scheduling for Lifetime Extension of Platform-Based MPSoC Designs", IEEE Transactions on Parallel and Distributed Systems, vol 22, pp. 2088-2099, Dec. 2011.
CSC1020: Hands-On Introduction to C++
CSC 1520: Computer Principles & C++ Programming
CENG3470: Digital Circuits
CSC3420: Computer Systems Architecture
ENGG2120B: Introduction to Digital & μP Systems
CENG 3420: Computer Design
