Haile Yu

Thought is already is late, exactly is the earliest time.

Short Biography

I obtained my BS degree in Chu Kochen Honors College, Zhejiang University, major in electrical engineering. Now I am a Phd candidate in Custom Computing Lab, Department of computer science and engineering, The Chinese University of Hong Kong, under supervision of Prof. Philip H.W. Leong (now in USYD, old webpage in CUHK) and Prof. Qiang Xu.

[6]	Eddie Hung, Steven J.E. Wilton, Haile Yu, Thomas C.P. Chau and Philip H.W. Leong . A Detailed Delay Path Model for FPGAs. In International Conference on Field-Programmable Technology (FPT), 2009 (to appear) [ pdf ] [ bib ]
[5]	H. Yu, P. H. W. Leong, H. Hinkelmann, L. Moller, M. Glesner, P. Zipf. Towards A Unique FPGA-Based Identification Circuit Using Process Variations. In International Conference on Field Programmable Logic and Applications (FPL), 2009 [ pdf ] [ bib ]
[4]	Haile Yu, Towards A Process Variation Aware Delay Model For FPGA Yield Enhancement. In International PhD Student Workshop on SOC, 2009 [ pdf ]
[3]	Haile Yu, Yuk Hei Chan, and Philip H.W. Leong. FPGA interconnect design using logical effort. In International Conference on Field Programmable Logic and Applications (FPL), 2008 [ pdf ] [ bib ]
[2]	Haile Yu. FPGA interconnect sizing using extended logical effort model. In International Conference on Field Programmable Logic and Applications (FPL), 2008 [ pdf ] [ bib ]
[1]	Haile Yu, Yuk Hei Chan, and Philip H.W. Leong. FPGA interconnect design using logical effort. In FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, pages 257-257, New York, NY, USA, 2008. ACM. [ bib ]