Jiang Li's Homepage

Background	Jiang Li is a PhD Candidate of Computer Science & Engineering at the Chinese University of Hong Kong. He received his B.E. degree in Computer Science & Engineering from Shanghai Jiaotong University, China in 2007 and MPHIL. degree in Computer Science & Engineering from the Chinese University of Hong Kong in 2010, respectively.
Research	Now Jiang Li is interested in test, design for test, yield enhancement and reliability issues in three dimensional integrated circuit.
Work Experience	Intern on Cisco CRDC as hardware engineer. Collaborate with Diagnosis planform sotware group, TDE group and manufacture together to find the root cause of board level faults and improve the diagnosis accuracy.
CV	My CV
Partner	Under supervision of Prof. Xu Qiang. Group Member: Y.Zhang,F.Yuan,X.Liu,L.Huang,R.Ye,Y.Liu,J.Zhang
Publication	Journal Paper [J1]. L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak, "Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3D SoCs under Pre-Bond Test-Pin-Count Constraint", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.PP, no.99, pp.1,July 2011.[PDF] Conference Paper [C6]. L. Jiang, Q. Xu, and B. Eklow, "On Effective TSV Repair for 3D-Stacked ICs", in Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Mar. 2012. [PDF] [C5]. Q. Xu, L. Jiang, H. Li, and B. Eklow, "Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges", in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2012. (invited paper) [PDF] [C4].L. Jiang, R. Ye and Q. Xu, "Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing across Dies", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.230--234 Nov. 2010. (Nominated for Best Paper Award, acceptance rate: 108/360 = 30.0%) [PDF][PPT] [C3].L.Jiang, Y. Liu, L. Duan, Y. Xie and Q. Xu, "Modeling TSV Open Defects in 3D-Stacked DRAM.", Proc. IEEE International Test Conference (ITC), paper 6.1, Nov. 2010. [PDF][PPT] [C2].L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak, "Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 191-196, Nov. 2009. (acceptance rate: 115/438 = 26.3%) [PDF][PPT] [C1].L. Jiang, L. Huang and Q. Xu, "Test Architecture Design and Optimization for Three-Dimensional SoCs", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 220-225, Apr. 2009. (acceptance rate: 226/965 = 23.4%) [PDF][PPT] Poster/Workshop　 [W2].L.Jiang, Q.Xu and Bill Eklow. "Yield Driven System Integration for 2.5D SoC." Workshop IEEE/ACM Design, Automation, and Test in Europe(DATE) , March. 2012. [W1].L.Jiang, Y.X. Liu and Q.Xu. "Modeling TSV Open Defects in Three-Dimensional Memory." Workshop IEEE/ACM Design, Automation, and Test in Europe(DATE) , Apr. 2010. Thesis　 L. Jiang,"Test Architecture Design and Optimization for Three-Dimensional System-on-chips". Master's Thesis. Department of Computer Science and Engineering. The Chinese University of Hong Kong. [PDF]
Finished Project	1. Test Architecture Design and Optimization on three dimensional system-on-chip [C1][C2]. 2. Test and Yield Enhancement on three dimensional DRAM [C3-4][W1]
On-Going Project	1. Yield Enhancement Techinque in 2.5D/3D IC [C4-C6]. 2. Board-Level Diagnosis
Teaching Assitants	CEG5020 Fault-Tolerant Computing CENG3420 Computer Design CENG3470 Digital Circuits CSCI1110 Introduction To Computing Using C++ CSCI1020 Hands-on Introduction to C++ ENGG2020 Digital Logic and Systems (Fall 201)